Rhythm It introduced its latest AI-powered Electronic Design Automation (EDA) platform called Verisium, which promises to ease the amount of time and resources that chipmakers put into the validation process.
The Santa Clara, California-based company said MediaTek and Samsung are among the first companies to use Verisium to identify errors in system-on-chip (SoC) designs and diagnose what causes errors.
Modern processors consist of billions of transistors that must fit into squares of silicon as small as a fingernail. How everything is arranged on the chip and how (and where) it is placed within a system affects metrics such as performance, energy efficiency, and even cost. As a result, Cadence has begun incorporating AI into more of its software tools to automate more aspects of the IC design process.
Verisium is a complement to its Cerebrus Intelligent Chip Explorer platform for AI-enhanced execution and Optimity Intelligent System Explorer To analyze the system level supported by artificial intelligence.
The purpose of verification is to identify and resolve chip design defects in the case of prefabrication. It is the final stage process to test the quality of the design and that everything inside is working as planned in the product.
The validation process usually begins after the slide design has been completed. The device is simulated with Hardware Description Language (HDL) code used to test the different SoC building blocks. The test platform effectively creates a virtual instance of a SoC that can be supplied with signals. Then, you can measure and evaluate the responses from the SoC to see if the internal SoC or IP has any issues.
Cadence said Verisium is working with its existing validation engines: Palladium for simulation, Protium for prototyping, Xcelium for simulation, Jasper for official validation, and Helium Virtual and Hybrid Studios.
Previously, you had to run each of these actuators separately for each step in the validation process – what Cadence calls a “single act, single actuator approach.” On the other hand, Verisium leverages big data and AI to optimize multiple runs of multiple engines across a full SoC design and realization campaign.
As SoC complexity continues to rise, the verification process tends to take more time and resources than any other silicon engineering task. Thus, says Cadence, verification is ripe for improvement with artificial intelligence.
Verisium is also on top of Cadence’s new “JedAI” platform, which collects massive amounts of data from the chip design process, analyzes it to identify areas for improvement, and even stores it for future use.
Cadence said JedAI is a platform in the sense that its AI-powered offerings — Verisium, Cerebrus, and Optimity — and third-party silicon lifecycle management systems sit on top of it. When it comes to using Verisium, its validation tools feed data arising from the validation process, from waveforms, coverages, and reports to log files, into the JedAI platform, where it is all stored and evaluated.
Then, JedAI builds machine learning models and mines other proprietary metrics from the data, and shares what it learns with the company’s Verisium to identify potential areas for improvement or root cause issues.
“Due to the massive increase in the volume and complexity of chip design over the past decade, the volume of design and verification data has also increased,” said Venkat Thanvantry, Cadence Vice President of Artificial Intelligence Research and Development. “Previously, we saw that once a chip design project was completed, valuable data was deleted to make way for the next project. There is valuable information in the legacy data, and the Cadence JedAI Platform makes it easier for engineering teams to access this knowledge and apply it to future designs.”
Customers can start using multiple apps when using Verisium. Some of them benefit from machine learning, both supervised and unsupervised, including reinforcement learning, while others do not.
- Verisium AutoTriage: Creates machine learning models that help automate the repetitive task of sorting failures to find the worst. To do this, it predicts test failure and ranks it with common root causes.
- Semantic difference vericium: It uses algorithms to compare source code reviews of full IP building blocks or SoCs. The app categorizes these reviews and ranks those most disruptive in system behavior to help identify potential bug hotspots.
- Verisium Waveminer: It applies AI engines to analyze waveforms from multiple checks and determine which signals are, at what times, most likely to represent the root cause of test failure.
- Vericium Pendown: Integrates with Cadence JedAI Platform and other industry-standard tools to build machine learning models of source code changes, test reports, and log files to predict which source code checks are most likely to cause failures.
- Verisium Correction: Natively integrated with the JedAI platform and other Verisium applications, this application uses artificial intelligence for root cause analysis purposes, along with supporting simultaneous and automatic comparison of pass and fail tests. The patching solution extends from IP to SoC and from single-boot verification to multi-boot verification.
- Verisium Manager: It brings a complete IP and SoC validation management solution at the IP and SoC level with multi-engine validation planning, job scheduling, and coverage on its JedAI platform. It uses artificial intelligence techniques to improve the efficiency of data center operation for verification. This app integrates directly with other Verisium apps from Cadence, opening the door to push-button deployment of the full Verisium platform from a unified browser-based management console.
Save time with artificial intelligence
Paul Cunningham, senior vice president and general manager of the system and verification division at Cadence, said Verisium will help chip companies make more informed decisions during the design and verification process. But the biggest impact seems to be on the productivity side of things.
The company said its customers are already using Verisium to sort failed tests three times faster than they did previously, while reducing the time it takes to identify the root cause of failure by up to 75%.
Given that error analysis and debugging account for 50% (or in some cases more) of the time chip companies devote to verification, Cadence claimed that Verisium’s AI-powered tool could lead to significant productivity improvements.